Digital electronic systems are ubiquitous. As solid state technology has advanced, shrinking feature size and concomitantly increasing both circuit density and operating speed, supply voltage levels have dropped. Lower supply voltage for digital circuits reduces current flow (switching current as well as losses such as leakage and crossbar currents), and hence power consumption. Reduced power consumption is important for reducing generated heat, which must be removed, such as by convection (cooling fans). Reduced power consumption is particularly important for portable electronic devices, to preserve battery life.
However, reducing the supply voltage to digital circuits may also limit their performance. For example, since switching current is the primary source of power consumption in CMOS technology, restricting the supply voltage in many cases restricts the achievable clock speed.
It is well known that, within one system, different circuits may operate optimally at different power supply voltage levels. For example, a memory circuit (e.g., DRAM, static RAM, flash, EEPROM) may operate at its maximum required speed with a relatively low supply voltage. On the other hand, a computational circuit (e.g., CPU, ALU, DSP, graphic or video processor) may require a higher supply voltage to achieve a desired level of performance, for example by running at a higher clock speed. Furthermore, an analog circuit, such as a radio transceiver, may have a digital interface operating at the analog voltage level, which may be higher or lower than the system digital circuits.
One approach to disparate supply voltage requirements within a system is the creation of “voltage islands,” or regions on a chip or circuit board that are supplied with a supply voltage level different than other islands, or regions. One problem with the conventional voltage island approach is that level shifters must be interposed on every signal (e.g., every data and address bit, and every control signal) that crosses an island boundary. Level shifters are required to preserve signal integrity in transition between circuits operating under different supply voltages—for example, a “high” signal level generated in a low-voltage island may be interpreted as a “low” value when received in a high-voltage island. Additionally, level shifters prevent low voltage gates from being directly driven with high supply voltages, which would cause excessive leakage energy. Level shifters necessarily take up silicon area, consume power, and introduce propagation delay in the shifted signal.
Level shifters may be designed to minimize their deleterious effects on system cost and performance. For example, FIG. 5 depicts a single-bit level shifter implemented with only six transistors. Such level shifters introduce little cost in small numbers, and many signals (e.g., control signals such as interrupts) are not on critical performance paths, and hence can tolerate the additional delay. It is the requirement of level-shifting entire data and address buses—which can span hundreds of bits and the delay of which may limit system performance—which stands as a primary challenge in implementing the voltage island approach to digital system design.
Driven by ever-larger quantities of data to be processed, and enabled by the development of burst-mode memory (e.g., DDR DRAM), many modern electronic systems have adopted a burst or frame model for system bus transactions. That is, many system buses define one or more durations (e.g., in terms of elapsed time or number of bus cycles) for which a system bus is dedicated to a particular intra-system data transfer. The receiving functional block then processes the received data, and may subsequently transfer data to another block, or to system memory.
As well known in the art, system buses are usually “tri-state,” meaning bus drivers may assume three states: a logic high, a logic low, and a high impedance state. In the high impedance state, circuits on the other side of the driver are electrically isolated from bus activity. Thus, in the data transfers described above, after receiving data in a burst transaction, a receiving block would tri-state, or electrically isolate itself from the bus, allowing the bus to engage in other data transfer operations while the receiving block processed the received data.